1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and fabrication methods for the same. In particular, it relates to the nonvolatile semiconductor memory used as a flash memory.
2. Description of the Related Art
An electrically erasable/writable read-only memory (EEPROM), for example, is known as a nonvolatile semiconductor memory. The EEPROM, more specifically NAND EEPROM, has a memory cell array including memory cells disposed on respective intersections of a plurality of word lines running along the row direction and a plurality of bit lines running along the column direction crossing to the word lines. The memory cells are generally made from stacked gate MOS transistors, each constructed by stacking a floating gate and a control gate, for example.
A NAND flash memory has a structure including a NAND string of a plurality of memory cell transistors connected in series and selector transistors disposed on both sides of the NAND string. Furthermore, element isolating regions are arranged in parallel to the column direction extending along the active regions of memory cells, configuring the memory cell array.
The nonvolatile semiconductor memory such as a flash EEPROM needs a high-voltage circuit region that provides high voltage pulses such as a write-in voltage, an intermediate voltage, and an erase voltage to a memory cell array region. Meanwhile, there is a low voltage circuit region required to operate at a high speed at a normal low voltage.
However, it is advantageous to use the low voltage transistors with enhanced driving capability operating at high-speed performance in the low voltage circuit region. In the low voltage circuit region of the flash EEPROM capable of operating at a low voltage, ensuring driving capability of transistors is particularly necessary.
Meanwhile, it is important to enhance the write-in and the read-out speed by lowering the resistance of word lines in a memory cell array region as the capacity of the memory cell array increases. A means for forming a metallic silicide film for word lines in the NAND flash memory may be used for suppressing delay in the word lines emanating from increased capacity of the memory and enhancing the operating speed.
In the low voltage circuit region, transistors with enhanced driving capability operating at high-speed performance are required. Furthermore, forming metallic salicide films on the gates and diffusion layers of the memory cell transistors is a method for decreasing the resistance of word lines in memory cell regions of a large capacity of memory cell array and thereby increasing write-in and read-out speed performance.
However, according to the nonvolatile semiconductor memory, such as a flash EEPROM, when metallic salicide films are formed on the gates and the diffusion layers of the transistors in all of the circuit regions as with CMOS logic circuits, suppression of increasing of a value of the junction leakage current and suppression of decreasing of a value of the junction breakdown voltage and the surface breakdown voltage is required for the high voltage transistors within the high voltage circuit region, which allows generation of the high voltage greater than the value of 15V, such as the write-in voltage Vpgm or the erase voltage Verase and so on.
Moreover, when metallic salicide films are formed on the gates and the diffusion layers in all of the circuit regions as with CMOS logic circuits, the value of resistance in the resistor elements may decrease, the resistor element area may increase, and the value of the gate breakdown voltage for transistors in a high voltage peripheral circuit may decrease.
As a solution, a method for forming metallic salicide films in selected areas may be used. However, the method brings about a difficulty in processing due to two types of areas: an area with the metallic salicide film and an area without the metallic salicide film.
In particular, since the NAND type flash memory requires the higher operational voltage than the AND type flash memory and the NOR type flash memory, problems with the junction leakage current and the junction breakdown voltage are more remarkable.
A nonvolatile semiconductor memory with a lowered resistance of word lines and having a capability of reading out from the memory cell transistor in a shorter time, which is attained by forming grooves on control gates extending along the word line direction, forming metal interconnects on an interlayer insulating film, embedding metal interconnects in the grooves, and thereby decreasing the value of the resistance of polycide word lines, and a fabrication method thereof have been disclosed (e.g., see Japanese Patent Application Laid-open No. 2000-100975).
A semiconductor memory capable of operating at high speed performance, which is attained by forming a silicide layer on gate electrodes without forming a silicide layer on the impurity diffused layers of memory cell transistors and then forming a silicide layer on gate electrodes and diffusion layers of transistors in a logic circuit region, and a fabrication method thereof have been disclosed (e.g., see Japanese Patent Application Laid-open No. 2003-347511).
Furthermore, a nonvolatile semiconductor memory including peripheral transistors, each characteristic of lowered resistivity of the wirings for the gate electrodes and the source/drain electrodes in the peripheral transistors, and memory cells occupying a smaller area, which is attained by forming a metallic silicide layer on both the diffusion layer of memory cell transistors and peripheral transistors and also on the gate electrode of the peripheral transistors, and further by providing memory cell transistors with a self-aligned contact structure, is disclosed (e.g., see Japanese Patent Application Laid-open No. 2002-217319).